1. Field of the invention
This invention relates to a read only memory, and more particularly to a read only memory for use in a semiconductor integrated circuit device which requires high speed operation.
2. Description of the prior art
As the operating speed of a microprocessor has made great progress in recent years, high speed operation is strongly required in a read only memory (referred to as ROM, below) which stores system programs and processing programs of the microprocessor. In other words, the reduction of access time which is from an address input to a data readout is highly required in the ROM.
FIG. 1 shows the structure of a ROM according to a prior art of this invention. As shown, this ROM is comprised of a memory cell matrix 101, a word line decoder 102, a column decoder 103, and an output buffer 104. In memory cell matrix 101, a plurality of word lines and bit lines are arranged in form of a matrix and a memory cell is placed at each intersecting point of the matrix. Word line decoder 102 decodes an address input having a plurality of bits so as to select a certain word line. According to said address input, column decoder 103 generates a column control signal and selects a certain bit line. And, output buffer 104 outputs stored data in a memory cell whose position is designated by a word line and a bit line selected with said word and column decoders.
FIG. 2 shows the detailed structure of memory cell matrix 101 and output buffer 104 of the prior art ROM (NOR type; n bits.times.32 words) which is of a precharge type. In this figure, the circuit structure of one bit is shown.
In FIG. 2, B0, . . . , and B3 indicate bit lines, and W0, . . . , and W7 indicate word lines. At each intersecting point of these bit and word lines, a memory cell comprised of an N-channel transistor is placed. Each one end of bit lines B0, . . . , and B3 is connected to a power supply VDD through N-channel transistor 111, . . . , or 114, each of which turns on or off by being controlled with a clock signal CLK. Each other end of bit lines B0, . . . , and B3 is connected to data line 119 through N-channel transistor 115, . . . , or 118, each of which is to select a column line and turns on or off according to column control signals C3, . . . , and CO. Data line 119 is connected to power supply VDD through P-channel transistor 120 which turns on or off by being controlled with the inverted clock signal -CLK. This data line 119 is also connected to the input of sense inverter 121 which produces output data OUT.
FIG. 3 shows the circuit structure of word line decoder 102 of the prior art ROM.
As shown in FIG. 3, word line decoder 102 is comprised of four inverters, eight 3-input NAND gates, and eight 2-input NOR gates.
The structure of column decoder 103 is almost the same as that of the present invention. For instance, a column decoder which is shown in FIG. 6 explained later may be used as column decoder 103.
The operation of the above mentioned ROM will be described below.
Once N-channel transistors 111, . . . , and 114 have turned on in synchronous with the rising of clock CLK, all the bit lines B0, . . . , and B3 are precharged. After the rising of clock CLK, the values of address inputs A0, . . . , and A4 are fixed. On the other hand, during level H of clock CLK, the inverted signal -CLK stays at level L. This allows P-channel transistor 120 to turn on and data line 119 to be precharged up to level VDD.
Let us consider one example in which word line W2 is selected by word line decoder 102 so as to select memory cell Z1. As shown in FIG. 2, there is no transistor connected to memory cell Z1. Then, bit line B2 is not discharged and transistor 117 is selected. As a result, sense inverter 121 gives "0" as output data OUT. On the contrary, if a transistor is connected to memory cell A1, bit line B2 is discharged, allowing sense inverter 121 to give "1" as an output.
As is obvious from the above mentioned explanation, in such the precharge ROM, the precharged value is output without any change when "0" is generated as output data. In this case, no substantial time delay is produced. In other words, signal delay arises only when a transistor connected to a memory cell turns on to discharge the bit line connected to the memory cell. In this case, the output from sense inverter 121 changes from "1" to "0".
According to the above mentioned reason, the logical threshold of sense inverter 121 is usually set at a relatively high value in said ROM, in which high speed operation is required, in order to quickly detect the output change from "1" to "0".
In the above mentioned ROM, however, one serious problem still exists.
Each transistor in the memory cell matrix connected to respective bit line B0, . . . , or B3, has a junction capacitance across its gate and the respective bit line. On a data readout, however, only one transistor is selected to discharge among other transistors connected to the same bit line. Accordingly, the Junction capacitance of the other transistors connected to the same bit line becomes considerably large at the data readout. This fact lowers the data readout speed.
The above mentioned disadvantage becomes more serious when a large number of transistors are used so as to increase the storage capacity of the ROM. As a result, a large capacity ROM having a capability of high speed data readout can hardly be realized in the prior art techniques.